Input voltage operation of an operational amplifier (op-amp) which can span rail-to-rail power supply potentials increases the useful range of input voltages over which the op-amp can operate. This is particularly useful for applications which have relatively low power supply rail potentials, such as hand-held electronic devices like cellular telephones and pagers.
Furthermore, providing the rejection of common-mode voltages that completely span the power supply rail potentials also contributes to the useful range of the op-amp. An op-amp must have extremely good common mode rejection in order to amplify a small differential voltage riding on a proportionally larger common-mode signal, while rejecting variations in the common-mode signal.
FIG. 1 shows a conventional op-amp input stage 12 which has been used to achieve the desired input voltage range and common-mode rejection range. A V.sub.cc power supply is connected+to a first terminal 10 and-to a ground terminal 11 to form the positive and negative supply rails. While a single V.sub.cc power supply is shown connected between the first terminal 10 and the ground terminal 11, double positive and negative supplies could be used. In the case of double positive and negative supplies, the midpoint of the two supplies would be considered the ground level.
An input stage 12 has negative and positive differential voltage input terminals 13 and 14 connected to the bases of first and second NPN differential transistors 20, 21, respectively, and to the bases of first and second PNP differential transistors 22, 23, respectively. That is, first and second NPN transistors 20, 21 and first and second PNP transistors 22, 23, are complementary long-tailed transistor pairs having commonly connected inputs.
The input stage input currents, from the collectors of the first and second NPN transistors 20, 21 or from the collectors of the first and second PNP transistors 22, 23 are combined in a dual-sided current subtractor 15. The dual-sided current subtractor 15 is shown in block form. One example of a dual-sided current subtractor may be found in a co-pending patent application, entitled RAIL TO RAIL OPERATIONAL AMPLIFIER INTERMEDIATE STAGE, Ser. No. 08/205,573, filed on even date herewith. In its basic form, first, second, and third subtractors 16, 17 and 18 of the dual-sided current subtractor 15 combine the input stage input currents to provide an input stage output current at terminal 19 that is a linear function of the differential input signal voltage at terminals 13 and 14. Thus, the input stage is a differential transconductance amplifier.
Back-to-back clamp diodes 27, 28 may be coupled between the bases of the NPN transistor pair 20, 21 and between the bases of the PNP transistor pair 22, 23 to limit the differential input drive to a peak-to-peak value of two diode drops. If the diodes 27, 28 are included, a pair of resistors 25, 26 are also included to couple the transistor bases to the input terminals 13 and 14 to isolate diodes 27 and 28 from the input terminals 13 and 14.
A bias circuit 24 sinks a tail current I.sub.3 for the NPN transistor pair 20, 21 and sources a tail current I.sub.2 to the PNP transistor pair 22, 23. This tail current control allows input stage operation over a common-mode input voltage range which is the power supply rail-to-rail.
The bias circuit 24, which will be discussed in detail below, proportions the input stage tail currents I.sub.2, I.sub.3 in accordance with the common mode input voltage. That is, when the common mode voltage is midway between the positive and negative supply rails, the tail currents are equal. As the common mode voltage swings lower, the tail current I.sub.3 decreases while the tail current I.sub.2 proportionately increases. When the common mode voltage falls close to the ground rail, transistors 20 and 21 cease to function as a differential pair, and the tail current I.sub.2 is double what it is when the common mode voltage is midway between the positive and negative supply rails. Thus, the input stage functions normally even when the common mode voltage is close to the negative supply rail.
Conversely, as the common mode voltage swings up toward the positive supply rail, the tail-current I.sub.2 decreases while the tail current I.sub.3 rises proportionately. As the common mode nears the positive supply rail, and transistors 22 and 23 cease to function as a differential pair, and the tail current I.sub.3 is double what it is when the common mode voltage is midway between the positive and negative supply rails. Thus, even when the common mode voltage is close to the positive supply rail, the input stage operates normally.
Put simply, the bias circuit 24 proportions the input stage tail currents I.sub.2, I.sub.3 as a function of common mode voltage, thereby maintaining constant transconductance even when the common mode voltage approaches either power supply rail.
The bias circuit 24 details are as follows. In the top half of bias circuit 24, PNP transistor 29 forms a current mirror with PNP transistor 30. A constant current source 31 passes a current I.sub.1, which flows in the collector of transistor 29 and in a resistor 32. While the current source 31 is also connected through resistor 32 to the bases of transistors 29 and 30, and to the base of a transistor 33, the base currents are negligible and are therefore disregarded.
The transistor 30 sources a current that is connected to the emitter of the transistor 33, which is usually off, and I.sub.2 (the current sourced by the PNP input transistor tail 22, 23). That is, because the current through transistor 29 is I.sub.1, and PNP input transistor 30 is part of a current mirror, the current through transistor 30 is also I.sub.1.
In the bottom half of the bias circuit 24, NPN transistor 34, current mirror transistor 35, series resistor 36 and NPN control transistor 37 are connected in a complementary fashion to the components in the top half of the bias circuit 24. That is, the current mirror transistor 35 sinks the NPN-transistor pair 20, 21 tail current I.sub.3, and a current I.sub.37 in NPN transistor 37. I.sub.37 in transistor 29, which is usually off. Transistor 34 receives I.sub.33, a current in PNP transistor 33. Put simply, the top-half bias circuit current mirror 29, 30 and the bottom-half bias circuit current mirror 34, 35 are cross-coupled through transistors 33 and 37.
When the common mode input voltage is at the rail-to-rail midpoint, I.sub.2 =I.sub.3 and both the transistor 33 and the transistor 37 are off. Due to the cross connections, I.sub.2 +I.sub.3 is a constant that is determined by I.sub.1. When I.sub.2 rises, I.sub.3 is reduced proportionately, and vice versa.
While the circuit of FIG. 1 extends the input common voltage range, it has the problem that when the input voltage at the positive input terminal 14 swings above the power supply rail V.sub.cc or below the power supply rail ground, the second NPN transistor, which in normal operation has an inverting output, becomes overdriven. In this overdriven state, the NPN transistor's collector-base parasitic diode outputs a non-inverting signal, and this non-inverting signal causes a phase reversal in the resultant collector current.
A further problem with the circuit of FIG. 1 is that substantially the full power supply voltage will be encountered at the emitters of the PNP transistors 30, and 37 over the rail-to-rail common mode input operating range. This problem can be addressed by using lateral geometry PNP transistors, which will not Zener. However, lateral geometry transistors are much slower than vertical geometry transistors.
Additionally, as the collector voltage of the transistors 30 and 35 reaches the supply rails, the collector impedance values of the transistors 30, 35 fall off due to the variance of V.sub.BE with collector-to-emitter voltage. This fall-off of collector impedance is known in the art as the Early effect and is discussed, for example, in Horowitz and Hill, The Art of Electronics. This Early-effect impedance value fall-off can potentially cause the tail currents I.sub.2 and I.sub.3 to be modulated.